1. Field of the Invention
This invention relates to an improved serial interface. More particularly, it relates to the elimination of a synchronization signal such as a frame sync signal in a synchronized serial data stream or a time division multiplex serial data stream by replacement with a synchronizing data protocol.
2. Background of Related Art
Serial communications are an effective method of communicating between two digital components, particularly in cost sensitive applications to minimize the hardware requirements otherwise required for parallel communications. For instance, a serial interface technique implementing a transmit line, receive line, data clock line, and a frame synchronizing line (and a reset line) has been implemented in conventional multipurpose codecs.
A codec is a device which for many years has allowed efficient and inexpensive digitization of telephone grade audio. The typical codec (short for COder-DECoder) is an integrated circuit or other electronic device which combines the circuits needed to convert analog signals to and from digital signals, e.g., Pulse Code Modulation (PCM) digital signals.
Early codecs converted analog signals at an 8 KHz rate into 8-bit PCM for use in telephony, and were not capable of handling modem inputs. More recently, the efficiency and low cost advantages of codecs have been expanded to convert analog signals at a 48 KHz sampling rate into 16-bit stereo (and even up to 20-bit stereo) for higher quality use beyond that required for telephony. With higher quality and broader bandwidth capability, today""s codecs find practical application with consumer equipment such as voice band modems.
With the development of codecs for these more sophisticated purposes came the need to improve the analog signal-to-noise (S/N) ratio to at least 75 to 90 dB. One major step toward achieving this high S/N ratio was accomplished more recently by separating the conventional codec into two individual sub-systems: a controller sub-system or integrated circuit (IC) handling primarily the digital interface to a host processor, and an analog sub-system or IC handling primarily the interface to, mixing and conversion of analog signals. This split digital/analog architecture has been documented most recently as the xe2x80x9cAudio Codec ""97 Component Specificationxe2x80x9d, Revision 1.03, Sep. 15, 1996 (xe2x80x9cthe AC ""97 Specificationxe2x80x9d). The AC ""97 Specification in its entirety is expressly incorporated herein by reference.
FIG. 3 shows a conventional split-architecture audio codec interfacing to a device such as a low speed voice band modem 510 in accordance with the AC ""97 Specification.
In particular, in FIG. 3, an AC controller sub-system 700 interfaces to an AC analog sub-system 702 via a five-wire synchronized serial data bus (i.e., a time division multiplexed (TDM) bus) referred to as the AC link 504. The five-wire TDM bus of the AC link 504 comprises a sync signal 712, a reset signal 520, a serial TDM data stream SDATA_OUT 716 from the AC controller sub-system 700 to the AC analog sub-system 702, a clock signal BIT_CLK 714, and a serial TDM data stream SDATA_IN 718 from the AC analog sub-system 702 to the AC controller 700. The clock signal BIT_CLK 714 is derived by a clock source 506 in or relating to the controller 700.
The circuitry in the conventional AC analog sub-system 702 which interfaces to an external analog device such as the low-speed voice band modem includes an analog-to-digital converter (ADC) 522 and a digital-to-analog converter (DAC) 524. The ADC 522 samples the analog modem signal input to the AC analog sub-system 702 and provides 16-, 18- or 20-bit data at 48 Ks/s to the AC link 504 for insertion into an appropriate time slot (e.g., time slot 5) of the serial TDM data stream SDATA_IN 718 input to the AC controller sub-system 700. Conversely, the DAC 524 receives 16-, 18- or 20-bit data from the serial TDM data stream SDATA_OUT 716 from the AC controller sub-system 700 of the AC link 504 and converts the same into an analog signal output to the low-speed voice band modem 510. Conventional demodulation and modulation techniques such as quadrature amplitude modulation (QAM) or Carrierless Amplitude and Phase (CAP) may be performed by a digital signal processor (DSP) and/or other processor in conjunction with the ADC 522 and/or DAC 524.
FIG. 4 depicts a conventional sync signal 712, serial TDM data stream SDATA OUT 716, and serial TDM data stream SDATA IN 718, in a twelve slot TDM bi-directional data stream between the analog and controller sub-systems 702, 700 of a split-architecture audio codec such as in accordance with the AC ""97 Specification. The twelve time slots 1 to 12 of the serial TDM data streams SDATA_OUT 716 and SDATA_IN 718 are framed by the conventional sync signal 712. The sync signal 712 is derived from a TAG Phase 600 received during time slot 0. All time slots are 20 bits wide.
The sync signal 712 synchronizes the reception and transmission of the SDATA_OUT 716 and SDATA_IN 718 with respect to clock signal BIT_CLK 714. This synchronization between the data lines and the clock signal is shown in more detail in FIG. 5.
In particular, FIG. 5 shows the clock signal BIT_CLK 714 and serial TDM data stream SDATA_OUT 716 with reference to the sync signal 712. The sync signal 712 is based on the clock signal BIT_CLK 714, which is a fixed 12.288 MHz clock signal.
FIG. 6 shows an implementation of the AC analog sub-system (i.e., codec) 702 interfaced with the controller 700 on a low voltage circuit side using a conventional differential implementation of the serial interface. As shown, the codec 702 is typically exposed to voltages in excess of the power voltage, and therefore is referred to herein as a high voltage circuit. In some situations it is desirable to AC couple a clock signal in a serial interface such that a codec or other high voltage circuit 702 may be electrically isolated from the ground of a low voltage circuit 700. It would similarly be desirable to AC couple the transmit data signal 716, the receive data signal 718, the frame sync signal 712, and the reset signal 520. If all signals between the low voltage controller 700 and the high voltage codec 702 are AC coupled, then there is essentially no need for a connection to exist between the ground of the low voltage controller 700 and the ground of the high voltage codec 702.
Unfortunately, in practical situations, once the grounds between the low voltage controller 700 and high voltage codec 702 are broken, a large common mode voltage may exist between the ground potential of the low voltage controller 700 and the ground potential of the high voltage codec 702. This large common mode voltage may interfere with the AC coupled digital signals in the isolated high voltage codec 702. Moreover, the cost of an isolating transformer 791 can be significant, and if the codec 702 is to perform impedance emulation with a central office, the transformer 791 can degrade impedance matching between the codec 702 and the telephone line.
Thus, an alternative implementation of the serial interface has been developed wherein the codec (which may be connected to a telephone line, modem, audio source, etc.) is placed in the high voltage section of the system as shown in FIG. 7 to eliminate the expensive and large transformer 791 which is otherwise traditionally used to couple the low voltage side to the high voltage side. This technique eliminates the need for the transformer 791, but is disadvantageous for other reasons, e.g., because it requires additional hardware such as the AC coupling capacitors C (typically rated at 3000 V AC).
An example of such a serial interface could be used with a LUCENT TECHNOLOGIES CSP1034 multi-processor mode SIO interface. In such an example, five serial lines are typically needed to provide the interface, and each of the five signals corresponding to the five serial lines would need to be converted to differential signal pairs. Each of the five signal pairs would each need to be isolated with a corresponding pair of capacitors for voltage isolation, requiring a total of ten (10) high voltage capacitors.
It is important to reduce the number of communication lines necessary to interface between circuits, particularly where one of the circuits is subject to higher voltages, e.g., a codec, because of the relative cost of the hardware and space required for each of the individual lines. Thus, there is a need for reducing the number of signal lines in a synchronous serial interface such as the time division multiplex (TDM) serial interface of the AC ""97 specification.
In accordance with the principles of the present invention, a synchronizing data protocol for use in occasionally synchronizing timing between a master device and a slave device comprises a preamble insertion module in the master timing device adapted to insert a preamble code word into a data stream for transmission to the slave device. A synchronizing preamble detection module in the slave device is adapted to detect a presence of the preamble code word in the data stream.
A method of synchronizing a slave device to a master device over a serial data bus in accordance with another aspect of the present invention comprises providing an interrupt signal to the slave device. The data stream received by the slave device is monitored for a presence of a synchronizing preamble code word. A timing in the slave device is based on a timing of a detection of the synchronizing preamble code word by the slave device.